Synergy Tier-1 distributor Jarwey｜Sub-aperture reload: SY2162QF 16-bit vs SY2640 64-bit shift window
Jarwey is a Synergy (Xinlijie) Tier-1 distributor for ultrasound HV switch ICs, and can help with selection, datasheets, samples, and lead time.
Each sub-aperture change on a linear probe has to finish inside the transmit-to-receive gap: the FPGA must clock a new pattern into the HV analog switch and latch it before the next pulse. The number that decides whether that gap is long enough is shift-register length divided by the clock you actually run, not the channel count on the front of the datasheet.
This note answers one question. At a 50 MHz shift-clock ceiling, how long is one full load on SY2162QF (16-bit register) versus SY2640 (64-bit register)? Bleed-versus-clamp and the SY2325/SY2326 logic-level split are separate articles.
Minimum load time is shift clocks only
Times below use bits / clock from the published register length and maximum shift clock. They are a lower bound for one serial fill. They are not a datasheet blanking spec. Latch (LE), clear (CLR), and board delay sit outside the column. If the FPGA clock is slower than the maximum, stretch the window by the real clock. Cascade devices by adding bits before you divide.
| Part | Shift register | Max shift clock | Full-load lower bound at that clock | Logic I/O |
|---|---|---|---|---|
| SY2162QF | 16-bit | 50 MHz | 16 / 50 MHz = 0.32 µs | 5 V CMOS |
| SY2640 | 64-bit | 50 MHz | 64 / 50 MHz = 1.28 µs | 3 V to 5 V CMOS |
| SY2160 | 16-bit | 20 MHz | 16 / 20 MHz = 0.80 µs | 3.3 V CMOS |
On the same 50 MHz clock, 64 bits take four times as long as 16 bits: 0.96 µs more before the latch. A gap of about 0.5 µs can hold one SY2162QF reload at the maximum clock. It cannot hold one SY2640 reload.
Which register length fits a short gap
- Only a handful of elements change, and the gap is under 1 µs. Start with SY2162QF (16-bit, 50 MHz). If you cascade a second device, add the bits. Do not keep the 0.32 µs figure.
- One package should cover a 64-element sub-aperture. Look at SY2640, and check that the PRI gap is longer than 1.28 µs plus latch. Package choice (BGA versus LGA) is a different article.
- The board shift clock is only about 20 MHz. A 16-bit load is then about 0.80 µs. That is the SY2160 class. Do not reuse the SY2162QF 50 MHz number.
Sub-aperture reload checklist
- Read the shift-register length from the datasheet. Do not substitute the headline channel count.
- Use the FPGA shift clock you will run, not the datasheet maximum, unless you truly clock at that maximum.
- Load time = bits / actual clock. Add bits first when devices are daisy-chained.
- Add latch pulse width and setup after the last clock. Add CLR cycles if you clear every frame.
- Place that total inside the TX/RX gap or the sub-aperture update slot, and confirm the latch completes before the next HV pulse.
- Check logic voltage separately: SY2162QF is 5 V CMOS; SY2640 is 3 V to 5 V.
- Measure on-resistance, off-isolation, charge injection, and the bleed path on the bench. A timing budget does not clear the receive noise floor.
Figures are for shortlist math. Confirm them on the current datasheet and on the board before production. This is not an unverified swap.
Datasheet, samples, and a second look at the gap
SY2162QF product page · SY2640 product page · SY2160 product page
Datasheet preview is on the product page. For the latest revision, samples, small lots, or a gap estimate against your element map, contact Jarwey.
Related: SY2162QF bleed versus clamp · SY2325 / SY2326 logic levels · SY2640 / SY2642 package split
Jarwey · Synergy Tier-1 distributor · kerry.w@jarwey.cn · Contact.
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