COSINE Tier-1 distributor Jarwey｜Motor feedback: COS620BRZ in-amp vs COS8552SR zero-drift op amp
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A servo or industrial drive feedback board usually carries two small signals that should not share one gain stage. Hall sensors, sin/cos encoders, and torque bridges produce differential millivolts plus cable common-mode. Phase current on a low-side shunt is often only tens of millivolts into a 5V ADC, and that resistor sits next to inverter heat. Name the two nets before you pick a part.
Put the differential sensor on the instrumentation amplifier COS620BRZ. Put a ground-referred shunt, with the ADC on the same 5V rail, on the zero-drift op amp COS8552SR. The INA129/AD620 cross-check, the AD8552 evaluation list, and the 5V zero-drift bandwidth ladder already exist. This note does not reprint them.
Which path gets which amplifier
| Path | Signal | Supply and common-mode | Start here | Page |
|---|---|---|---|---|
| Hall / sin-cos encoder / torque bridge | Differential millivolts, cable common-mode | About 4.5–36V, CMRR matters | COS620BRZ in-amp | 864 |
| Low-side shunt, 5V ADC | Tens of millivolts full scale, drift-sensitive | 1.8–5.5V, RRIO | COS8552SR zero-drift op amp | 865 |
| High-side shunt above 5.5V | Out of scope here | Above the COS8552SR rails | Current-sense amp or 36V precision op amp | Current sense |
High-side or wide-supply current loops are covered in the current-sense family and the COS4177SR note. The 36V in-amp matrix is the existing family table. Gain-resistor math for COS620BRZ stays in the earlier COS620BRZ article and the datasheet.
Datasheet numbers that decide this split
Only the figures that change the path choice are listed. Limits and test conditions are in the PDF. Recheck them on the board.
- COS620BRZ: SOP-8. Offset about 50µV max, drift about 0.2µV/°C typical, GBW about 1.5MHz, supplies about ±2.25V to ±18V, CMRR about 125dB, quiescent current about 1mA. One external resistor sets gain. Closed-loop bandwidth falls as gain rises, so compare it with the sensor, not with the current loop.
- COS8552SR: dual zero-drift, SOP-8. Offset about 2µV typical, drift about 0.005µV/°C, about 55µA per channel, 1.8V to 5.5V, RRIO. It fits a low-side shunt that shares the 5V ADC domain. Input common-mode has to stay inside the rails.
Checklist before layout freeze
- Name both nets. Hall, sin/cos, or torque bridge is one path. The shunt is the other. Do not ask one stage to own both error budgets.
- Where is the common-mode? Cable or a 12/24V field points to COS620BRZ. A ground-referred shunt and a 5V ADC point to COS8552SR. A shunt on a bus above 5.5V is a different shortlist.
- Full-scale millivolts. Use the in-amp gain resistor to land the bridge or Hall span in the ADC. Use the COS8552SR feedback network for the shunt span, and confirm the RRIO output is not clipping.
- Heat next to the inverter. Put the 50µV / 0.2µV/°C class and the 2µV / 0.005µV/°C class into the angle or current error budget, then measure the assembled board. A datasheet class is not a board result.
- Split the bandwidth. COS620BRZ GBW is about 1.5MHz and shrinks with gain — match the sensor. COS8552SR covers DC and low-frequency error. A faster current loop belongs with the 10MHz or 25MHz precision op amps.
- Layout. Kelvin the shunt. Add an input RC on the in-amp against PWM edges. Keep both input pairs off the gate-drive loop.
- Datasheets and samples. Download the PDFs from the product pages. Ask Jarwey for samples and lead time. Board validation is required. This is not an unverified pin swap.
Datasheets and contact
Jarwey · COSINE Tier-1 distributor · kerry.w@jarwey.cn · Contact.
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