CETC Tier-1 distributor Jarwey｜650V SiC in flyback: WM3HA160065E clamp, body diode and TO-252 thermal budget-JARWEY

CETC Tier-1 distributor Jarwey｜650V SiC in flyback: WM3HA160065E clamp, body diode and TO-252 thermal budget

Jarwey 3 2026-09-16 09:36:03

When a 650 V SiC MOSFET goes into a flyback or quasi-resonant stage—adapters, auxiliary supplies, industrial AC-DC—the blocking questions are rarely "is SiC better than superjunction". They are concrete: does the RCD clamp need re-tuning, is the body-diode forward drop acceptable, and does a TO-252 surface-mount package carry the thermal budget.

This article works through those using WM3HA160065E (650 V / 160 mΩ / TO-252, CETC 55th Institute G3 technology, datasheet downloadable): voltage class first, then thermal path and gate drive. The silicon-superjunction cross-reference table and the cost / lead-time / 15V-0V adoption gates are covered in the replacement-path article and the three-gates article; they are not repeated here.

Jarwey is a Tier-1 distributor of CETC (CETC 55 / Guiji Nanfang) SiC power devices—selection support, datasheets, sampling & small batch, lead-time coordination.

Pick the voltage class before the on-resistance

In a flyback the switch sees bus voltage + reflected voltage N·(V_out+V_f) + leakage-inductance spike. On universal input (85–265 VAC) the rectified bus sits near 375 V, reflected voltage is typically 100–150 V, and the clamped spike adds another 50–100 V. A 650 V class part works, but the headroom is adequate rather than generous. With a PFC front end (400 V bus) or heavy input transients, the 900 V class is the calmer choice.

Only after that should output power and thermal budget drive the R_DS(on) pick. Reversing the order is how designs end up with a very low on-resistance part sitting right on its voltage limit.

Part	V_DS	R_DS(on) typ @15 V drive	Package	Flyback use case to evaluate first	Product page
WM3HA160065E	650 V	~160 mΩ (I_D@25℃ ~20 A)	TO-252	Higher-power flyback / forward, SMD copper-plane cooling	6
WM3HA300065E	650 V	~300 mΩ (I_D@25℃ ~10 A)	TO-252-2L	Low/mid-power auxiliary supplies, load switching	869
WM3HA330090E	900 V	~330 mΩ (I_D@25℃ ~11 A)	TO-252-2L	Post-PFC bus, or flyback with harsh input transients	868

All three are G3 devices rated for 15 V / 0 V gate drive, so the output of most flyback controllers drives them directly—no negative-rail turn-off supply required. Confirm every number against the datasheet on the product page.

Four items a flyback design must re-budget

RCD clamp energy. Faster switching means steeper di/dt and a sharper leakage spike edge. Clamp R/C values carried over from the silicon design are usually too soft; re-tune against the measured spike and check the clamp diode's recovery speed.
Body-diode forward drop. SiC body diodes typically show a higher V_f than silicon MOSFETs. Wherever the topology freewheels through the body diode (synchronous rectification, active clamp, bridge auxiliary paths), budget that loss separately instead of reusing the silicon estimate. The upside is very low Q_rr, which helps hard-switched turn-on loss and EMI.
dv/dt and current-sense noise. Steeper edges mean the CS leading-edge blanking, Y-capacitor return and transformer shield coupling all need re-checking. The usual symptom is false triggering or cycle skipping at light load.
TO-252 thermal path. An SMD package cools through the PCB copper, so thermal resistance depends on plane area, via array and neighbour spacing. Once switching loss drops, conduction loss and copper-plane capability are usually what caps output power.

Flyback power-stage checklist (7 items before board bring-up)

Voltage stress. Maximum bus + reflected voltage + measured spike against the 650 V or 900 V rating—is the margin enough?
Drive conditions. Controller output level and source/sink current within the datasheet window (+15…+18 V on, 0…−5 V off).
Gate resistors. Re-optimise turn-on/turn-off resistance for the EMI versus switching-loss trade-off; do not reuse the silicon values.
Clamp network. Re-tune RCD components and clamp diode against the measured leakage spike.
Freewheel path. Determine whether current flows through the body diode; if it does, recompute loss and temperature rise with the SiC V_f.
Thermal budget. Measure case and copper-plane temperature at full load and high ambient; verify the via array is in place.
Samples and records. Request the datasheet revision, samples and lead time from Jarwey; freeze the BOM only after bench and thermal-cycling results.

These are verification steps, not a drop-in swap. A similar footprint does not imply identical switching behaviour.

What Jarwey supports

Aligned with mainstream 650–900 V SMPS requirements, with no compromise on blocking capability or gate-drive compatibility. No negative-rail supply keeps the drive BOM simple and makes the silicon-to-SiC conversion cost controllable. Sampling and small batch, lead-time coordination and project-level follow-up are available for power-supply makers piloting efficiency and power-density upgrades.