Synergy Tier-1 distributor Jarwey｜Latch enable is pin LE on SY2160, not the LEB on +5 V switches-JARWEY

Synergy Tier-1 distributor Jarwey｜Latch enable is pin LE on SY2160, not the LEB on +5 V switches

Jarwey 6 2026-11-04 10:42:53

Jarwey is a Tier-1 distributor for Synergy (Xinlijie) ultrasound ICs, and can help with selection, datasheets, samples, small lots, and lead time.

Do not name the probe-switch latch net from a sibling product page. The SY2160 and SY2320FN datasheets call that pin LE. The +5 V switch datasheets call it LEB. Only some product pages print those three letters. A page that never says LEB is not evidence that the pin is named LE.

Bleed resistance, the clamp switch, the thermal flag, and the shift-register window already have their own notes. This one is only the latch-enable name and pin. The SY2160 and SY2320FN PDFs are marked preliminary. SY2162 is Rev. 0.1, September 2023. Lock the BOM to the revision Jarwey sends.

What the page prints, and what the pin table calls it

Part	Product-page text	Datasheet name	Pin	CLR	Page
SY2160	Mentions a latch. Does not print LE or LEB	LE	Pin 9	Pin 22	856
SY2320FN	Mentions a latch. Does not print LE or LEB	LE	Pin 7	CLR is in the pin table; pin number not cited here	855
SY2162QF	Prints “LEB, CLR”	LEB	Pin 21	Pin 22	853
SY2322	Does not print LEB	LEB	Named LEB; pin number not cited here	CLR is in the pin table	858
SY2326	Does not print LEB	LEB	Pin 84	Pin 42	860
SY2325	Prints “LEB, CLR”	LEB	Pin 84	Pin 42	859
SY2640	Prints “LEB, CLR”	LEB	Ball F1	Ball G3	857
SY2642	Prints “LEB, CLR”	LEB	Pin 108	Pin 37	861

SY2160 and SY2162QF are both 48-pin parts, and CLR is pin 22 on both. The latch enable is not the same pin: pin 9 is LE on SY2160, pin 21 is LEB on SY2162QF. Do not copy by pin number.

The polarity sentences point the same way. The net name still changes.

On SY2160 and SY2320FN the logic notes say: the rising edge of LE leaves each switch in its latched state; while LE is low, shift-register data flows through the latch; while LE is high, further clocks do not change the switches; CLR overrides the other inputs. The AC section is headed VDD = 5.0 V. The row “Set up time before LE rises” shows 25 ns in the minimum column at 0°C, 25°C, and 70°C, and a dash in the maximum column. A following line is marked VDD = 3.0 V and does not show 25. That line is not quoted here.

The +5 V overview says to hold LEB high while data is shifted in, then pulse LEB low to load the latch. The pin function is active-low: high holds the data, low latches it. The SY2162 notes match that shape: the rising edge keeps the latched state, clocks do nothing to the switches while LEB is high, and CLR wins. Use the table above for the name and the pin. The sentence direction is not a netlist.

Latch-pin checklist

Open the pin table of the exact orderable. Do not name the net from a sibling product page.
On SY2160 and SY2320FN the latch-enable net is LE. Those two pages print neither LE nor LEB.
The +5 V datasheets use LEB. SY2322 and SY2326 omit the letters on the product page. That omission does not rename the pin to LE.
High holds, low passes data into the latch, the rising edge keeps the latched state, and CLR overrides. Check that logic table in the PDF before the FPGA pin is tied.
Do not paste a pulse width from the SY2162 timing table onto SY2160. The only number cited here is the 25 ns minimum setup on SY2160 and SY2320FN under the VDD = 5.0 V heading.
LE / LEB is not the thermal flag THP and not the clamp control CSW. Those pins stay in their own notes.
Against a Microchip, Hitachi, or Maxim high-voltage switch, compare the latch-pin name and polarity, then measure on the board. This is an evaluation, not an unverified drop-in. The current PDFs are linked below. For a later revision, samples, or a small-lot date, contact Jarwey.