Jarwey GaN Tier-1｜TP65H035 800 V is a spike note: continuous rating stays 650 V-JARWEY

Jarwey GaN Tier-1｜TP65H035 800 V is a spike note: continuous rating stays 650 V

Jarwey 7 2026-10-29 15:38:46

Jarwey provides GaN tier-1 support for selection and lead time. The key-spec box on these 650 V SuperGaN FETs prints VDSS(TR) 800 V. The absolute-maximum table still lists continuous drain-source voltage at 650 V, for junction temperature from −55 °C to 150 °C. The 800 V number is an off-state spike, and the footnote is a different sentence on each part.

Main question: can TP65H035G4WS, TP65H050G4WS, and TP65H150G4PS take an 800 V DC bus because the cover prints 800 V? No. On the 035 datasheet the non-repetitive 800 V spike must be shorter than 30 ms, and a second row sets repetitive transient voltage at 750 V with a spike shorter than 5 µs. On the 050 and 150 datasheets the 800 V spike must be shorter than 30 µs. Pasting the 30 ms note from the 035 sheet onto the other two parts stretches the allowed spike by about a thousand times.

Use 035 / 050 when the power stage is a bridgeless totem-pole PFC. Use 150 for adapters, low-power SMPS, and lighting. Settle this footnote before comparing on-resistance. The 35 mΩ / 50 mΩ split, the 150 mΩ adapter note, the 0 V gate-off network, and the 150 °C dynamic on-resistance stay in those articles.

What 800 V means on each datasheet

Part	Continuous VDSS	Transient row	Off-state footnote	Datasheet	Page
TP65H035G4WS TO-247, source tab	650 V TJ −55 °C to 150 °C	Non-repetitive 800 V, plus a repetitive row at 750 V	Non-repetitive spike shorter than 30 ms. Repetitive 750 V spike shorter than 5 µs. The cover key-spec box prints 800 V only	v3.6 2024-01-08	12
TP65H050G4WS TO-247, source tab	650 V TJ −55 °C to 150 °C	800 V, one row. No 750 V repetitive row	Duty D < 0.01, spike shorter than 30 µs, non-repetitive	1v1 2022-03-06	427
TP65H150G4PS TO-220, source tab	650 V TJ −55 °C to 150 °C	800 V, one row. No 750 V repetitive row	Spike shorter than 30 µs, non-repetitive. That footnote states no duty cycle	Rev.3.00 2025-11-25	852

The 035 and 050 PDF headers say the specifications can change. Open the PDF on the product page and match the revision before you quote a number. Gate absolute maximum is ±20 V on all three parts. That rating does not license the drain spike. Recommended gate resistance and the 0 V turn-off network are in the earlier article.

Bus-voltage checklist (7 items)

Split the two voltages. Continuous operation stays inside 650 V. 800 V exists only inside the off-state spike footnote.
Keep the pulse width on its own part. Shorter than 30 ms belongs to the non-repetitive 800 V row of TP65H035G4WS. TP65H050G4WS and TP65H150G4PS say shorter than 30 µs.
750 V is only on the 035 sheet. The repetitive 750 V row, spike shorter than 5 µs, is in that absolute-maximum table. The 050 and 150 tables have no such row.
Duty cycle is printed on the 050 sheet. D < 0.01 is that footnote. The 150 footnote of 30 µs does not add a duty cycle, so do not borrow the 050 sentence.
Ringing on every switching cycle is a repetitive event. On TP65H035G4WS the repetitive row is 750 V and shorter than 5 µs, which is a different row from 800 V / 30 ms.
Keep the earlier scene split. Evaluate 035 / 050 for bridgeless totem-pole PFC. Evaluate 150 for adapters, low-power SMPS, and lighting. This note does not redo on-resistance.
Samples and revision. Ask Jarwey for the datasheet revision that matches the product page, plus samples, a small lot, and the lead time. Freeze the bus after the scope shows spike width and whether the spike repeats.