GaN Tier-1 distributor Jarwey｜Keep SuperGaN off at 0 V: gate-loop split for TP65H035, TP65H050, TP65H150-JARWEY

GaN Tier-1 distributor Jarwey｜Keep SuperGaN off at 0 V: gate-loop split for TP65H035, TP65H050, TP65H150

Jarwey 2 2026-10-06 15:38:13

Jarwey is a Tier-1 channel for these GaN power devices, and can support selection, datasheet revision control, samples, and lead time.

A negative gate-off rail built for a SiC MOSFET does not belong on these three 650 V SuperGaN FETs by default. TP65H035G4WS, TP65H050G4WS, and TP65H150G4PS are normally-off cascodes: a high-voltage GaN HEMT in series with a low-voltage silicon MOSFET. Each datasheet lists V_GSS at ±20 V. Threshold is 3.3 V min / 4 V typ / 4.8 V max on all three, but the test current is not the same (1 mA, 0.7 mA, and 5 mA). R_DS(on) rows are taken at V_GS = 10 V.

The on-resistance split by power class is already published for bridgeless totem-pole PFC and for the 150 mΩ adapter class. This note only answers which gate-loop numbers to copy from which PDF.

Copy the gate loop from that part’s datasheet

Part	What the PDF actually says	External gate network	Q_G typ	Package	Page
TP65H050G4WS datasheet 1v1, 2022-03-06	Printed line: recommended gate drive (0 V, 12 V) with R_G = 30 Ω. The switching-time row is separate: V_GS 0→10 V, R_g = 45 Ω, I_D = 22 A.	Ferrite bead 200–300 Ω at 100 MHz. DC-link RC snubber is required: [4.7 nF + 8 Ω] × 2, next to the drain pin. A switch-node snubber is called out only if R_G is below the recommendation.	16 nC (24 nC max) V_DS = 400 V, V_GS 0→10 V, I_D = 22 A	TO-247, source tab, G-S-D	427
TP65H035G4WS datasheet v3.6, 2024-01-08	No “(0 V, 12 V)” recommended-drive sentence. The hard-switching table sets R_G(OFF) to 30 Ω and names Si823x/Si827x or similar. Switching-time test: V_GS 0→12 V, R_G = 30 Ω, I_D = 32 A.	Single resistor: R_G(OFF) = 30 Ω. Dual: 15 Ω / 30 Ω, or effective 10 Ω / 30 Ω. Bead 180–270 Ω at 100 MHz. Gate-source resistor 10 kΩ. DC link [4.7 nF + 5 Ω] × 2 or [10 nF + 2.3 Ω]. The same table lists operating frequency < 100 kHz.	22 nC V_DS = 400 V, V_GS 0→10 V, I_D = 32 A	TO-247, source tab, G-S-D	12
TP65H150G4PS datasheet Rev.3.00, 2025-11-25	No recommended-R_G table in the same format. Switching-time conditions are V_GS 0→12 V, R_G = 70 Ω, bead 240 Ω at 100 MHz, I_D = 10 A. 70 Ω is a test condition, not a design value.	Do not drop in the 30 Ω network from the TO-247 parts, and do not treat 70 Ω as the recommended resistor. Close R_G, bead, and snubber on the bench against this part’s application note.	8 nC V_DS = 400 V, V_GS 0→10 V, I_D = 10 A	TO-220, source tab, G-S-D	852

The <100 kHz row belongs only to the TP65H035G4WS hard-switching network table. It is not a frequency ceiling for TP65H050G4WS or TP65H150G4PS. A faster design has to re-check resistor, DC-link snubber, and switch-node snubber.

Reverse-recovery charge is also part-specific. TP65H035G4WS lists Q_RR typ 0 nC at I_S = 32 A, V_DD = 400 V, di/dt = 1000 A/µs, and notes that Q_OSS is excluded. TP65H050G4WS lists Q_RR typ 120 nC at I_S = 22 A, V_DD = 400 V. TP65H150G4PS describes reverse recovery as negligible and does not print the same Q_RR row.

The tab is source, not drain

Ordering information marks the package configuration as Source on all three. TP65H035G4WS and TP65H050G4WS are 3-lead TO-247; TP65H150G4PS is TO-220. Pin order is G-S-D and the tab is source. A heatsink insulator laid out for a drain-tab silicon MOSFET moves both the gate return and the creepage. That is a layout check, not a drop-in replacement.

Seven checks before the layout freezes

Off level. Is the driver already at 0 V off, or is it a SiC negative rail? Absolute maximum is ±20 V. Do not sit on that limit.
On bias. R_DS(on) is specified at 10 V. TP65H050G4WS explicitly recommends (0 V, 12 V). The other two switching-time tests also swing from 0 V to 12 V; only TP65H150G4PS lacks a recommended resistor table.
Resistor and bead. Take them from that PDF. On TP65H050G4WS the recommended 30 Ω and the 45 Ω switching-time resistor are different rows.
TP65H035G4WS frequency row. The hard-switching table says <100 kHz. Above that, re-qualify the network.
The 70 Ω on TP65H150G4PS. Test condition only. Do not copy 30 Ω across from the TO-247 devices.
Turn-off spike. Use that part’s V_DSS(TR) note. On TP65H035G4WS, non-repetitive 800 V is a spike shorter than 30 ms, and repetitive 750 V is shorter than 5 µs. On TP65H050G4WS, 800 V also requires duty < 0.01 and a spike shorter than 30 µs. On TP65H150G4PS, 800 V is non-repetitive and shorter than 30 µs. Those are not one shared 800 V budget.
Samples and revision. PDFs are on the product pages. Archive the revision, then ask Jarwey for samples and lead time before the BOM is frozen.