GaN Tier-1 distributor Jarwey｜650V GaN FET TP65H035G4WS: 72 mΩ typical at 150°C-JARWEY

GaN Tier-1 distributor Jarwey｜650V GaN FET TP65H035G4WS: 72 mΩ typical at 150°C

Jarwey 4 2026-10-22 15:36:05

Jarwey is a tier-1 channel for these GaN power devices and can help with selection, datasheet revision control, samples, and lead time.

The milliohm figure on a 650V SuperGaN cover is the 25°C dynamic on-resistance. TP65H035G4WS is 35 mΩ typical / 41 mΩ max, TP65H050G4WS is 50 / 60 mΩ, and TP65H150G4PS is 150 / 180 mΩ. All three rows are at V_GS=10V. At T_J=150°C, same bias, the typical values are 72 mΩ, 105 mΩ, and 307 mΩ. Hot conduction loss uses that row.

The 25°C split for totem-pole power is already in the PFC note and the adapter note. Gate voltage versus a 15V SiC MOSFET is the 15 October note. Gate resistor, ferrite bead, and 0V turn-off are the 6 October note. This page keeps the hot R_DS(on), junction-to-case thermal resistance, and the 100°C continuous current.

Dynamic on-resistance at 150°C, and thermal resistance

Part	25°C dynamic R_DS(on)	150°C typical	R_θJC typical	Continuous I_D / dissipation	Page
TP65H035G4WS v3.6, 8 Jan 2024 TO-247, source tab	35 typical / 41 max mΩ V_GS=10V, I_D=30A	72 mΩ same V_GS and I_D no maximum at this temperature	0.8 °C/W R_θJA typical 40 °C/W, no board condition stated	I_D 46A at T_C=25°C, 29A at 100°C P_D=156W at T_C=25°C	12
TP65H050G4WS 1v1, 6 Mar 2022 TO-247, source tab	50 typical / 60 max mΩ V_GS=10V, I_D=22A	105 mΩ same V_GS and I_D no maximum at this temperature	1.05 °C/W R_θJA typical 40 °C/W, no board condition stated	I_D 34A at T_C=25°C, 22A at 100°C P_D=119W at T_C=25°C	427
TP65H150G4PS Rev.3.00, 25 Nov 2025 TO-220, source tab	150 typical / 180 max mΩ V_GS=10V, I_D=10A	307 mΩ same V_GS and I_D no maximum at this temperature	1.5 °C/W R_θJA typical 50 °C/W, board note on the thermal table	I_D 16A at T_C=25°C, 10A at 100°C P_D=83W at T_C=25°C	852

Dividing the typical rows gives 72/35≈2.06, 105/50=2.10, and 307/150≈2.05. That ratio is arithmetic on the published typicals. The datasheets do not state a temperature coefficient. Each row is dynamic R_DS(on), and each sheet says the parameter is 100% production tested.

Thermal resistance and current stay on their own lines. Typical R_θJC is 0.8, 1.05, and 1.5 °C/W. Continuous drain current at T_C=100°C is 29A, 22A, and 10A, against 46A, 34A, and 16A at 25°C. Maximum power dissipation at T_C=25°C is 156W, 119W, and 83W. Those three sets come from three datasheets. The 35:50:150 nameplate ratio does not scale them.

Junction-to-ambient figures are not on one shared note. The two TO-247 sheets list 40 °C/W typical and stop there. TP65H150G4PS lists 50 °C/W typical, with a thermal-table note: one-layer epoxy PCB, source connection, vertical, no forced air, 6 cm² copper, 70 μm copper. The TO-247 sheets do not carry that board note.

The continuous-current notes on TP65H035G4WS and TP65H050G4WS point at the circuit-implementation page. High-current gate parts stay on that page and on the 6 October gate note.

Six checks before the layout freezes

Temperature row. Conduction loss uses the 150°C typical dynamic on-resistance: 72 / 105 / 307 mΩ. The cover numbers 35 / 50 / 150 mΩ are at 25°C.
Maximum. The 25°C maxima are 41 / 60 / 180 mΩ. The 150°C rows publish a typical only.
Current. The on-resistance test currents are 30A / 22A / 10A, all at V_GS=10V. Continuous rating is a different line: 29A / 22A / 10A at T_C=100°C.
Thermal resistance. Typical R_θJC is 0.8 / 1.05 / 1.5 °C/W. The R_θJA board condition is written on TP65H150G4PS.
Revision. v3.6 (8 Jan 2024), 1v1 (6 Mar 2022), Rev.3.00 (25 Nov 2025). The PDF on the product page is the ordering copy.
Samples. Datasheets download from the product pages. Ask Jarwey for revision filing, samples, and lead time, and freeze the BOM after the bench.