CETC Tier-1 distributor Jarwey｜1200V SiC suffix L, K, or N: WM2HA020120L, WM2HA020120K, and WM2HA240120N are not one MOSFET

A 1200V SiC MOSFET suffix is a package and a current bin, not a cosmetic option. On the Guiji Nanfang Version 3.0 sheets, WM2HA020120L and WM2HA020120K share one 20mΩ electrical table and do not share a pinout. WM2HA240120N is a 240mΩ TO-263-7H device. It is not the surface-mount twin of the 20mΩ parts.

Bus-voltage choice between 650V and 1200V is already covered in the bus-split note. This note starts after the rail is already a 1200V G2 design.

Jarwey is a Tier-1 distributor for silicon-carbide power devices from China Electronics Technology Group Corporation’s Guiji Nanfang (the 55th Research Institute). CETC is the group mark. Guiji Nanfang is the subordinate unit.

Read the on-resistance test row before the package letter

All three are G2 devices with V_DS 1200V at V_GS=0V, I_D=100μA. Absolute maximum gate voltage is −10/+23V. Recommended operation is −5/+18V. Total gate charge is 217nC typical on L and K (800V, −5/18V, 32A) and 17.5nC typical on N (same gate swing, 5A). Threshold is listed as 2.0/2.8/4.0V on each sheet, but L and K use I_D=20mA and N uses I_D=1.4mA.

L and K match on the resistance table and miss on pin 2

Ratings, on-resistance, gate charge, and junction-to-case thermal resistance line up between WM2HA020120L and WM2HA020120K in Version 3.0. The outlines do not. On the four-lead part, pin 2 is Driver Source — the gate-loop return — pin 3 is Power Source, and pin 4 is Drain. On the three-lead part, pin 2 is Drain. A footprint drawn for one of them lands the gate return and the power loop on the wrong nodes of the other.

Driver Source is there so gate current does not share the power-source copper. It is not an extra source pad to flood together with Power Source at the package. The sheets do not offer an unverified swap.

N is not a 20mΩ TO-263

The middle of WM2HA240120N is 240, not 020. Quote 240mΩ typical / 312mΩ max only at V_GS=18V and I_D=5A. The 175℃ point on that row is 360mΩ typical. A second row at V_GS=15V and I_D=5A (295mΩ typical, 380mΩ max) is a test condition. It is not a 15V/0V flyback-controller feature. Recommended gate drive on these three G2 parts stays −5V off and +18V on. Parts whose features line actually says 15V/0V are the G3 TO-252 devices, such as WM3HA160065E, and they are outside this comparison.

Power dissipation is 78W for N and 517W for L/K, both at case 25℃ and junction 175℃. Thermal resistance is 1.95℃/W versus 0.29℃/W. A seven-lead surface-mount outline does not inherit the current or the heatsink budget of the TO-247 pair.

Seven checks before the layout is frozen

1. The DC bus is already in the 1200V class. This table does not choose 650V or 900V.
2. The loss model needs either 20mΩ at 18V/60A or 240mΩ at 18V/5A. N does not drop into the L/K conduction equation.
3. A three-lead TO-247 footprint expects Drain on pin 2. That points to K, not L.
4. On L, return the gate to pin 2 and run load current from pin 3. Do not short Driver Source to Power Source in a pour at the package.
5. On N, pin 4 is Drain, pin 2 is Driver Source, and pins 3, 5, 6, and 7 are Source.
6. Size the driver for −5/+18V and stay inside −10/+23V absolute maximum. Do not copy a 15V/0V rail from a G3 flyback MOSFET.
7. Confirm the datasheet revision, samples, and lead time with Jarwey. A similar package is not an unverified replacement.

Datasheets and product pages

• WM2HA020120L · PDF
• WM2HA020120K · PDF
• WM2HA240120N · PDF

Equivalent-spec wafer die available for order.